Nano-electronics research center imec announced today at SEMICON West that it has demonstrated concept and feasibility for pore-sealing low-k dielectrics in advanced interconnects. The method, based on the self-assembly of an organic monolayer, paves the way to scaling interconnects beyond N5.
Today, at SEMICON WEST 2015 (San Francisco), world-leading nano-electronics research center imec and Besi, a global equipment supplier for the semiconductor and electronics industries announced that they have jointly developed an automated thermocompression solution for narrow-pitch die-to-wafer bonding, a method by which singulated dies are stacked onto bottom dies which are still part of a fully intact 300mm wafer. The solution features high accuracy and high throughput, paving the way to a manufacturable 2.5D, 3D, and 2.5D/3D hybrid technology.
Imec and SPTS Technologies, an Orbotech Company, Collaborate on Critical Processes for 3D IC Wafer Stacking
Nano-electronics research center imec and SPTS Technologies, an Orbotech company (NASDAQ: ORBK) and supplier of advanced wafer processing solutions for the global semiconductor and related industries, announced today at SEMICON West that they are jointly developing a highly accurate, short cycle-time dry silicon removal and low temperature passivation solution for through-silicon via-middle processing and thinning of the top-wafer in wafer-to-wafer bonding.
Today, imec and Holst Centre (set up by imec and TNO) are demonstrating the most advanced smart garment to date at the Imec Technology Forum (ITF) in Brussels. The smart t-shirt measures a highly accurate electrocardiogram (ECG), recognizes activity and calculates energy expenditure in an unobtrusive way. The smart t-shirt allows for maximum user comfort and natural movement.
At this week’s VLSI 2015 Symposium in Kyoto (Japan), imec reported new results on nanowire FETs and quantum-well FinFETs towards post-FinFET multi-gate device solutions.
Liesbet Van der Perre, directeur bij imec academy en Professor aan de KU Leuven, ontving verleden vrijdag ( 29 mei 2015) in het Zweedse Lund een eredoctoraat voor haar belangrijke wetenschappelijk bijdrage aan de ontwikkeling van draadloze communicatietechnologieën en haar bijzondere inzet om door samenwerking binnen Europa, tussen universiteiten, onderzoeksinstellingen en de industrie, innovatie te stimuleren en nieuwe generaties radiotechnologie te ontwikkelen.
Fujifilm and imec demonstrate full-color organic light-emitting diodes with photoresist technology for organic semiconductors
FUJIFILM Corporation (President: Shigehiro Nakajima) (hereafter, “Fujifilm”) and nano-electronics research institute, imec (CEO: Luc Van den hove), have demonstrated full-color organic light-emitting diodes (OLED)*1 by using their jointly-developed photoresist technology*2 for organic semiconductors, a technology that enables submicron*3patterning. This breakthrough result paves the way to producing high-resolution and large organic Electroluminescent (EL) displays and establishing cost-competitive manufacturing methods.
Het Leuvense nano-elektronica onderzoekscentrum imec en het Amerikaanse Johns Hopkins University gaan samen met Marc Coucke, Michel Akkermans en de Vlaamse investeringsmaatschappij PMV, miDiagnostics oprichten voor de ontwikkeling van miLab.
Imec and Tokyo Electron Demonstrate Electrical Advantages of Direct Cu Etch Scheme for Advanced Interconnects
Today, at the IEEE IITC conference, nano-electronics research center imec and Tokyo Electron Limited (TEL) presented a direct Cu etch scheme for patterning Cu interconnects. The new scheme has great potential to overcome resistivity and reliability issues that occur while scaling conventional Cu damascene interconnects for advanced nodes.
During the IEEE IITC conference in Grenoble, the nanoelectronics research center imec and Lam Research Corporation today presented a novel bottom-up prefill technique for vias and contacts. The technique, based on Electroless Deposition (ELD) of Cobalt (Co) is a highly selective method resulting in void-free filling of via and contact holes. Potentially increasing the circuit performance, it is a promising path to scaling advanced interconnects and enabling future logic and DRAM nodes at the 7 nm node and below.